Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor

ABSTRACT

This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

The current application claims a foreign priority to application inChina 200910202080.8 filed on Dec. 31, 2009.

FIELD OF THE INVENTION

This invention belongs to one type of bipolar transistor (BJT). Moreparticularly it relates to one type of collector of bipolar transistor.

BACKGROUND OF THE INVENTION

A conventional bipolar transistor is illustrated in FIG. 1. PNP bipolartransistor has same structure as NPN bipolar transistor, with onlyreverse impurity type of every parts of device. NPN bipolar transistoris illustrated here as example. N type heavily doped region 11 is abovep type substrate 10. N type epitaxy layer 12 (doping level is lower thanburied layer 11, normally medium or low doped) is above heavily doped nburied layer 11. There are a few shallow trench isolation (STI)structures 13 a/13 b/13 c/13 d among n type epitaxy layer 12. The bottomof these STI is in contact with buried layer 11. N type heavily dopedregion 14 exists between STI 13 a/13 b or 13 c/13 d inside epitaxy layer12, which is used as collector reach through (sinker). P type base 15 ison top of n type epitaxy layer 12. Base 15 is semiconductor material,such as silicon, silicon germanium alloy, etc. It is connected to basepick up B. Heavily doped T-shape poly silicon is on top of base 15. Itis connected to emitter pick up E. In all, n type emitter 16, p typebase 15, n type epitaxy layer 12 and n type buried layer 11 formed NPNbipolar transistor vertically.

In bipolar transistor illustrated in FIG. 1, n type epitaxy layer 12between STI 13 b and 13 c is collector of the bipolar transistor. Thecollector picks up to C through n type heavily doped buried layer 11(collector buried layer) and n type heavily doped sinker 14. Thecollector buried layer area is large by this approach. Consequently theparasitic capacitance with substrate is also large. A deep trenchisolation structure 130 a/130 d is commonly formed under STI 13 a/13 dwhich surround entire bipolar transistor. Deep trench isolationstructure 130 a/130 d extend through n type heavily doped buried layer11 until inside p type substrate 10. It cuts through n type heavilydoped layer 11, in order to reduce junction area of collector buriedlayer to p type substrate 10, and reduce parasitic capacitance betweenthem.

FIG. 1 is only illustration of a bipolar transistor. There may bevariations of each portion during real manufacturing.

Following process steps are normally adopted for collector and buriedlayer of above mentioned bipolar transistor:

Step 1: n type impurity is ion implanted into p type substrate. Thecommonly used n type impurities are Phosphorus (P), Arsenic (As),Antimony, etc. N type heavily doped buried layer 11 is formed then.

Step 2: N type epitaxy layer 12 is grown (deposit one layer of n typesingle crystal 12) on top of n type heavily doped buried layer 11. Thedoping level of 12 is lower than heavily doped buried layer 11.

Step 3: Shallow trench was etched inside silicon. The depth of shallowtrench is normally below 2 um. The position of shallow trench is shownin FIG. 1 as 13 a/13 b/13 c/13 d.

A deep trench is then etched at the bottom of STI which encloses entirebipolar transistor. The depth of deep trench is normally more than 7 um.The position of deep trench is indicated as 130 a/130 d in FIG. 1.

Dielectric such as silicon (SiO₂) is then filled into shallow trench.The shallow trench isolation structures 13 a/13 b/13 c/13 d are formed.

N type epitaxy layer 12 between STI 13 b/13 c is the collector.

There are a few disadvantages of this approach of forming collector andburied layer of above bipolar transistor. First, the cost of growing ntype single crystal 12 on top of silicon substrate 12 is high. Second,the depth of deep trench isolation structure 130 a/130 d is more than 7um. Etch and fill in process are complex and expensive.

SUMMARY OF THE INVENTION

It is therefore an object of present invention to offer a manufacturingapproach of collector and buried layer of one type of bipolartransistor. There is no process of buried layer and epitaxy.

Following process steps are included in the manufacturing approach ofcollector and buried layer of bipolar transistor.

Step 1: Shallow trench 20 a, 20 b is etched on silicon substrate 20. Thedepth of the trench is less than 2 um.

Step 2: The bottom of above stated STI 20 a/20 b is doped with n typeimpurity by method of ion implantation. A doped region 21 a/21 b in thesubstrate 20 is formed near the bottom of above stated STI 20 a/20 b.

Step 3: Dielectric is filled into above stated shallow trench 20 a/20 b.Shallow trench isolation 22 a/22 b is then formed.

Step 4: The wafers undergo high temperature anneal process. Abovementioned doped area 21 a/21 b merges between STI 22 a/22 b throughlateral diffusion. Pseudo buried layer 21 is formed.

The pseudo buried layer 21 is collector buried layer of above mentionedbipolar transistor.

Step 5: The silicon substrate between STI 22 a/22 b and above pseudoburied layer go through single or multiple ion implantation. The abovementioned active region 20 is converted into doped region 23.

The doped region (23) is the collector of the bipolar transistor. Thedoping level should below that of pseudo buried layer 21.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and the object, features, and advantages of the inventionwill be apparent from the following detailed description of theinvention, as illustrated in the accompanying drawings, in which:

FIG. 1 is conventional bipolar transistor structure cross section view;

FIG. 2 is collector and buried layer of present invented bipolartransistor;

FIGS. 3 a˜3 d are step by step illustration of manufacturing approach ofcollector and buried layer of present invented bipolar transistor.

FIG. 4 presents an illustration of dopant concentration of collectorburied layer of present invention.

EXPLANATION OF THE LABELS

10: P type substrate; 11: N type heavily doped buried layer; 12: N typeepitaxy layer; 13a/13b/13c/13d: Shallow trench isolation structure130a/130d: Deep trench isolation; 14: N type heavily doped region; 15:Base; 16: Emitter; 20: Silicon substrate; 20a/20b: Shallow trench;21a/21b: Doped zone; 21: Pseudo buried layer; 22a/22b: Shallow trenchisolation 23: Doped region. structure; C: Collector pick up; B: Basepick up; E: Emitter pick up;

DETAILED DESCRIPTION OF THE INVENTION

Refer to FIG. 2, silicon substrate 20 of present invented bipolartransistor includes:

Shallow trench isolation structure 22 a/22 b, the active region betweenshallow trench isolation region 22 a/22 b is the collector of bipolartransistor.

Pseudo buried layer 21, lies at the bottom of STI region 22 a/22 b, iscontinuous between 22 a/22 b (merge together instead of two separateregions). Above stated pseudo buried layer is the collector buried layerof the bipolar transistor.

Doped region 23 is the active region between 22 a/22 b and above pseudoburied layer 21. The doping level of 23 is less than that of pseudoburied layer 21. Doped region 23 is the collector of bipolar transistor.

For NPN bipolar transistor, above stated substrate 10 is p type. Pseudoburied layer 21 and doped region 23 are all n type. For PNP bipolartransistor, above stated substrate 10 is n type. Pseudo buried layer 21and doped region 23 are all p type.

The collector and buried layer of invented bipolar transistor followsthe process steps as below (take NPN bipolar transistor as example, justrevert the doping type to get PNP bipolar transistor):

Step 1: refer to FIG. 3 a, shallow trench 20 a/20 b is etched usingconventional approach. The depth of the trench is less than 2 um. Fromtop view, shallow trench 20 a/20 b is just like 2 parallel line of arectangle.

Steps to get a shallow trench isolation (STI) process normally include:

Step 1.1, thin SiO₂ layer is grown thermally on silicon surface. ThisSiO₂ layer is called pad oxide. It is used to protect active region fromchemical contamination when silicon nitride (Si₃N₄) is removed insubsequent process.

Step 1.2, Si₃N₄ is deposited on silicon surface. Si₃N₄ is a harddielectric material used here as hard mask. It is used to protect theactive region when perform STI dielectric fill-in and use as a stoplayer in subsequent chemical-mechanical polish (CMP) process.

Step 1.3, photo resist is coated on silicon surface, followed byexposure and develop step. An etch window is exposed.

Step 1.4, Si₃N₄ and SiO₂ are etched away, and partial of siliconsubstrate is also etched away. Shallow trench is formed. Si₃N₄ and SiO₂stated in step 1.1/1.2 is the hard mask 30 that covers silicon substrate20 in FIG. 3 a.

Step 2: refer to FIG. 3 b, n type impurity is ion implanted into thebottom of shallow trench 20 a/20 b. Heavily doped n type region 21 a/21b is formed near the bottom of shallow trench 20 a/20 b of siliconsubstrate 10. Two doped region 21 a/21 b between shallow trench 20 a/20b have not connected yet. They are two separate regions instead.

After shallow trench is etched, a thermal grown oxide is commonly grownon shallow trench sidewall and bottom. This silicon oxide calls lineroxide. It is used to improve the interface characteristics betweenshallow trench silicon and the dielectric filled. This liner oxide isvery thin which have no impact to ion implantation.

Step 3: refer to FIG. 3 c, dielectric is filled into shallow trench 20a/20 b and shallow trench isolation structure 22 a/22 b is formed. Thedielectric used is normally silicon oxide (SiO₂), silicon nitride(Si₃N₄), silicon nitride oxide (SiOxNy, x/y is integer).

The process in forming STI also includes:

Step 3.1, a layer of dielectric such as silicon oxide is filled in. Thedielectric should at least fill in shallow trench fully.

Step 3.2, silicon wafer is polished using chemical-mechanical polishprocess. The filled dielectric should be in same height as silicon topsurface.

Step 3.3, Si₃N₄ is removed by wet etch process.

Step 4, refer to FIG. 3 d, thermal anneal process is carried out for thewafer, two heavily doped regions 21 a/21 b diffuse laterally andvertically. The lateral diffusion results in link of two heavily dopedregion 21 a/21 b. between shallow trench isolation structure 22 a/22 b.Pseudo buried layer 21 is then formed. The n type heavily doped region21 is the collector buried layer of whole bipolar transistor.

In FIG. 3 d, as main part (Si₃N₄ deposited in step 1.2) of hard mask 30is removed, hard mask is no longer illustrated in FIG. 3 d. The padoxide grown in step 1.1 is not shown in FIG. 3 d as it is too thin.

Step 5, refer to FIG. 2, single or multiple n type impurity ion implantis performed to substrate 10 which is between STI 22 a/22 b and on topof pseudo buried layer 21. Silicon substrate active region 10 is thenconverted into n type. The doping level is less than that of pseudoburied layer 21. The doped region 23 is the collector of whole bipolartransistor.

In step 2, ion implantation should be carried out in high dose lowenergy method. The so called “high dose” is 1×10¹⁴˜1×10¹⁶ per squarecentimeter. Phosphorous, Arsenic, Antimony can be chosen as n typeimpurity. Boron, Boron Fluoride can be chosen as p type impurity. Theion dose is 1×10¹⁴˜1×10¹⁶ per square centimeter. Indium can also bechosen as p type impurity, the ion implantation dose is 1×10¹⁴˜1×10¹⁶atom per square centimeter (or ion dose per square centimeter). The “lowenergy” stated above means ion implant energy less than 30 keV.

In step 4 stated above, high temperature anneal choose rapid thermalanneal (RTA) process.

In step 5 stated above, ion implantation should be carried out in mediumto low dose. The so called “medium to low dose” means ion implantationdose is generally less than 1×10¹⁴ atom per square centimeter (or iondose per square centimeter).

1. A manufacturing process for a collector and an n-type buried layer ofa bipolar transistor comprises, Step 1: etching a shallow trench on asilicon substrate wherein depth of the trench is less than 2 um; Step 2:doping bottom of the STI with an impurity by ion implantation; forming adoped region in a substrate near the bottom of the STI; Step 3: fillingdielectric into the shallow trench to form a shallow trench isolation;Step 4: annealing the above wafers with a high temperature; linking thedoped region with the STI through lateral diffusion to form a Pseudoburied layer; Step 5: implanting an active region between the STI andabove the Pseudo buried layer by single or multiple ion implantation toconvert the active region into a doped region, wherein the dopeconcentration of the doped region should below that of pseudo burylayer, and the doped region is a collector of the bipolar transistor. 2.The manufacturing process for a collector and a n-type buried layer of abipolar transistor of claim 1 comprise: for a NPN bipolar transistor, inthe step 1, the silicon substrate is p-type, in the step 2, the n-typeimpurity is implanted, heavily doped n-type regions are formed, in thestep 4, n-type heavily doped pseudo buried layer is formed, in step 5,n-type impurity is implanted and n-type doped region is formed; for PNPbipolar transistor, in the step 1, silicon substrate is n-type, in thestep 2, p-type impurity is implanted, heavily doped n-type regions areformed, in the step 4, p-type heavily doped pseudo buried layer isformed, in the step 5, p-type impurity is implanted and p-type dopedregion is formed.
 3. The manufacturing process of a collector and an-type buried layer of a bipolar transistor of claim 1 comprise, in thestep 2, ion implant is carried out in high dose, low energy, forPhosphorous, Arsenic, Antimony, Titanium, Indium, the ion dose is1×10¹⁴˜1×10¹⁶ per square centimeter; for Boron, Boron Fluoride, the iondose is 10¹³˜1×10¹⁶ per square centimeter, and the low energy statedabove means ion implant energy is less than 30 keV.
 4. The manufacturingprocess of a collector and a n-type buried layer of a bipolar transistorof claim 1 comprise: in the step 2, high dose low energy impurityimplant is performed to silicon substrate between STI, and three dopedregion is formed in silicon substrate; in the step 4, the above statedtwo doped regions can link together to form pseudo buried layer in abovestated STI structure by lateral diffusion.